This invention relates to a test pattern generating apparatus which generates test patterns for testing a logic circuit such as a semiconductor integrated circuit, and especially to a test pattern generating apparatus wherein test patterns from a storage device are transferred and stored in an unused block of a pattern generator when part of a logic circuit test equipment is broken down.
In testing a logic circuit, a test pattern is supplied to the logic circuit under test, and the resulting output from the logic circuit is compared with an expected pattern to determine whether the logic circuit works correctly or not. The pattern length and the word length of the test pattern and the expected pattern supplied to the logic circuit under test increase with increase in scale and density of the logic circuit under test. For example, for testing a logic circuit having 256 pins, a test pattern including the expected pattern is required to have a 256-bit word. Further, the pattern length for testing a 64K memory, for example, needs to be 3.times.64K.sup.2 steps in an algorithmic test pattern, such as in galloping and walking test patterns. Further, the test patterns are required to be generated with high speed in view of to the recent developments in speed of the logic circuits which are to be tested.
The test pattern as above cannot be directly generated by a storage device as is usually employed in a CPU system. Therefore, in a logic circuit test equipment there are provided a storage device of large capacity and relatively low speed, such as a disc memory, and a pattern generator of high speed, relatively small capacity and large word length. The test patterns including the expected pattern are previously provided from the storage device in predetermined amounts, and stored in the pattern generator, since a pattern generator of large capacity and high speed is very expensive. When testing the logic circuit, the pattern generator supplies the test pattern to the logic circuit under test and the expected pattern to comparators for evaluating the outputs from the logic circuit.
FIG. 1 shows a block diagram of a general construction of a logic circuit test equipment of this kind. A storage device 1 which has a large capacity of storage locations provides in advance test patterns and expected patterns to a pattern generator 2. The pattern generator 2 generates test patterns 13 and expected patterns 14 in parallel to each other when testing a logic circuit. The test patterns are supplied to a group of formatters 3 in which the test patterns are shaped to predetermined logic waveforms such as return-to-zero (RZ), non-return-to-zero (NRZ) waveforms and so forth. The test patterns delivered by the formatter 3 are provided to a group of drivers 4 which determine the voltage levels of the test patterns according to a logic circuit 5 that is being tested. The test patterns from the group of drivers 4 are supplied to a group of terminals 11 of the logic circuit 5.
Outputs from a group of terminals 12 of the logic circuit 5 are supplied to a group of logic decision circuits 7 for determining whether the outputs are at high or low logic level. The results from the group of logic decision circuits 7 are fed to a group of logic comparators 6 whose other input terminals are supplied with corresponding expected patterns 14 from the pattern generator 2. Thus the logic comparators 6.sub.1 to 6.sub.n compare the respective outputs from the group of logic decision circuits 7 with the expected patterns and provide the comparison results to a bus line 10 which is connected to a central processing unit (CPU, not shown). When there is any difference between the signals from the logic circuit 5 being tested and the expected patterns, the logic circuit 5 is rejected.
The storage device 1 stores test patterns by dividing each word of the test patterns into a plurality of blocks each of which has a plurality of bits, for example 16 bits for each block, and provides the divided test patterns to the pattern generator 2 before beginning a test. The data is set in the storage device 1 by means of programming. In FIG. 1 each word of the test patterns is divided into three successive blocks, for instance the first 48-bit word is divided into blocks a, b and c, the second word is divided into blocks d, e and f . . . , with each block having a 16-bit length. The blocks of each word of the test pattern from the storage device 1 are stored in corresponding blocks 17, 18 and 19 of the test pattern generator 2 as in FIG. 1.
In this way the test patterns are transformed and stored in the pattern generator 2 by predetermined amounts, so that the test patterns can be generated during the test one word at a time. Thus test patterns with large-bit words can be generated sequentially at high speed by accessing the pattern generator 2, since the pattern generator 2 has high speed and a large-bit word memory.
However, in this logic circuit test equipment, in the event of a defect arising in the circuit components, such as in the formatters, drivers, comparators, etc. or in the blocks of the pattern generator 2, the logic circuit test has to be stopped until the defect is repaired. When testing a logic circuit which has a smaller number of terminals than the maximum number of terminals which can be accommodated by the logic circuit test equipment, the test equipment has unused blocks in the pattern generator and also in the other circuit components. Accordingly, there is a possibility of testing the logic circuit without repairing the abovesaid defect by changing the portions of the test patterns, that is originally intended to be stored in a block of the test pattern generator corresponding to the defective part, to an unused block of the pattern generator 2; and of changing the corresponding circuit connection of the formatters and the like to the unused ones by using switches, for instance. However, for doing this, it is necessary to alter the contents in the storage device 1 for supplying and storing the test pattern in the unused blocks of the pattern generator 2, and thus quite a long time is required for programming.